Cadence SPB OrCAD 16.5.015 (Allegro SPB) Hotfix x32 | 567MB
Cadence OrCAD PCB design suites combine industry-leading, production-proven, and highly scalable PCB design applications to deliver complete schematic entry, simulation, and place-and-route solutions. With these powerful, intuitive tools that integrate seamlessly across the entire PCB design flow, engineers can quickly move products from conception to final output.
To keep pace with market demand for more performance and functionality in today’s mobile phones, digital cameras, computers, automotive systems and other electronics products, manufacturers pack billions of transistors onto a single chip. This massive integration parallels the shift to ever-smaller process geometries, where the chip’s transistors and other physical features can be smaller than the wavelength of light used to print them.
Designing and manufacturing semiconductor devices with such phenomenal scale, complexity and technological challenges would not be possible without electronic design automation (EDA). It is essential for everything from verifying that the myriad transistors do what the designer intended to dealing with physical effects on electrons traveling miles of wires with widths sometimes measuring less than 100 nanometers.
Cadence Design Systems is the world's leading EDA company. Cadence customers use our software, hardware, and services to overcome a range of technical and economic hurdles.
New Allegro 16.5 Technology
The latest Allegro technology will be available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB designers benefits such as:
- Higher functional density with a constraint-driven flow for embedded components
- Faster timing closure with new PCB interconnect design planning technology
- Fewer physical prototype iterations with concurrent team design authoring
- More efficient low-power design with integrated power delivery network analysis
- A compliant and faster implementation path with package/board-aware SoC IP
- Smoother collaboration among global teams with new SiP distributed co-design
- Flexibility through “base plus options” configurations
Fixed in Cadence SPB OrCAD 16.5.015
DATE: 02-03-2012 HOTFIX VERSION: 015
CCRID PRODUCT PRODUCTLEVEL2 TITLE
871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager
921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension
941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning
961646 PDN_ANALYSIS EMVIEWER EMViewer Help ] About shows wrong version
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.
970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances
972568 CONSTRAINT_MGR UI_FORMS Tools ]Excel missing from CM
972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized
973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value
973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
974533 SIP_LAYOUT OTHER Crashes in Edit ] Die Properties and obviously has a setup problem.
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
Name: Cadence SPB OrCAD
Version: 16.5.015 (Allegro SPB) 32bit Hotfix
OS: Windows XP / Vista / Seven
Platform: Cadence SPB/OrCAD 16.50.000 - 16.50.014
OS: Windows XP / Vista / Seven